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| march 2001 1/68 rev. 1.2 ST10R172l 16-bit low voltage romless mcu datasheet n high performance 16-bit cpu l cpu frequency: 0 to 50 mhz l 40ns instruction cycle time at 50-mhz cpu clock l 4-stage pipeline l register-based design with multiple variable register banks l enhanced boolean bit manipulation facilities l additional instructions to support hll and operating systems l single-cycle context switching support l 1024 bytes on-chip special function register area n memory organisation l 1kbyte on-chip ram l up to 16 mbytes linear address space for code and data (1 mbyte with ssp used) n external memory interface l programmable external bus characteristics for different address ranges l 8-bit or 16-bit external data bus l multiplexed or demultiplexed external address/data buses l five programmable chip-select signals l hold and hold-acknowledge bus arbitration support n one channel pwm unit n fail safe protection l programmable watchdog timer l oscillator watchdog n interrupt l 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (pec) l 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns n timers l two multi-functional general purpose timer units with 5 timers l clock generation via on-chip pll, or via direct or prescaled clock input n serial channels l synchronous/asynchronous l high-speed-synchronous serial port ssp n up to 77 general purpose i/o lines n no bootstrap loader n electrical characteristics l 5v tolerant i/os l 5v fail-safe inputs (port 5) l power: 3.3 volt +/-0.3v l idle and power down modes n support l c-compilers, macro-assembler packages, emulators, evaluation boards, hll- debuggers, simulators, logic analyser disassemblers, programming boards n package l 100-pin thin quad flat pack (tqfp) st10 core dpram interrupt controller p.4 p. 1 p.0 po.2 p.6 p.3 dedi cated pins asc gpt1/2 &pec wdt xssp p.5 osc pll p. 7 pwm 1
2/68 table of contents 68 1 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 interrupt and trap functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 hardware traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 pwm module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13 power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3/68 table of contents 15.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15.3.1 cpu clock generation mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15.3.2 memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 15.3.3 multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 15.3.4 demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.3.5 clkout and ready /ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.3.6 external bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.3.7 external hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.3.8 synchronous serial port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 16 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 17 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/68 ST10R172l - pin description 1 pin description figure 1 tqfp-100 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100999897969594939291908988878685848382818079787776 p5.13/t5in p5.14/t4eud p5.15/t2eud v ss xtal1 xtal2 v dd p3.0 p3.1/t6out p3.2/capin p3.3/t3out p3.4/t3eud p3.5/t4in p3.6/t3in p3.7/t2in p3.8 p3.9 p3.10/txd0 p3. 11/ rxd0 p3.12/bhe/wrh p3.13 p3.15/clkout p4.0/a16 p4.1/a17 p4.2/a18 p1h.6/a14 p1h.5/a13 p1h.4/a12 p1h.3/a11 p1h.2/a10 v ss v dd p1h.1/a9 p1h.0/a8 p1l.7/a7 p1l.6/a6 p1l.5/a5 p1l.4/a4 p1l.3/a3 p1l.2/a2 p1l.1/a1 p1l.0/a0 p0h.7/ad15 p0h.6/ad14 p0h.5/ad13 p0h.4/ad12 p0h.3/ad11 p0h.2/ad10 p0h.1/ad9 p0h.0/ad8 p5.12/t6in p5.11/t5eud p5.10/t6eud p7.3/pout3 p7.2 p7.1 p7.0 p2.11/ex3in p2.10/ex2in p2.9/ex1in p2.8/ex0in p6.7/breq p6.6/hlda p6.5/hold p6.4/cs4 p6.3/cs3 p6.2/cs2 p6.1/cs1 p6.0/cs0 nmi rstout rsti n v dd v ss p1h. 7/ a15 p4.3/a19 v ss v dd p4. 4/a20/ sspce1 p4. 5/a21/ sspce0 p4. 6/a22/ sspdat p4.7/a23/sspclk rd wr /wrl ready/ ready ale ea v dd v ss rpd p0l.0/ ad0 p0l.1/ ad1 p0l.2/ ad2 p0l.3/ ad3 p0l.4/ ad4 p0l.5/ ad5 p0l.6/ ad6 p0l.7/ ad7 v dd v ss ST10R172l 1 5/68 ST10R172l - pin description symbol pin number (tqfp) input (i) output (o) kind 1) function p5.10 Cp5.15 98-100 1- 3 i i 5s 5s 6-bit input-only port with schmitt-trigger characteristics. port 5 pins also serve as timer inputs: 98 i 5s p5.10 t6eud gpt2 timer t6 ext.up/down ctrl.input 99 i 5s p5.11 t5eud gpt2 timer t5 ext.up/down ctrl.input 100 i 5s p5.12 t6in gpt2 timer t6 count input 1 i 5s p5.13 t5in gpt2 timer t5 count input 2 i 5s p5.14 t4eud gpt1 timer t4 ext.up/down ctrl.input 3 i 5s p5.15 t2eud gpt1 timer t2 ext.up/down ctrl.input xtal1 xtal2 5 i 3t xtal1: input to the oscillator amplifier and internal clock generator 6 o 3t xtal2: output of the oscillator amplifier circuit. to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. observe minimum and maximum high/low and rise/fall times specified in the ac characteristics. table 1 pin definitions 1 6/68 ST10R172l - pin description p3.0 C p3.13 p3.15 8-21 22 i/o i/o 5t 5t a 15-bit (p3.14 is missing) bidirectional i/o port. port 3 is bit- wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 3 outputs can be configured as push/ pull or open drain drivers. the following pins have alternate functions: 9 o 5t p3.1 t6out gpt2 timer t6 toggle latch output 10 i 5t p3.2 capin gpt2 register caprel capture input 11 o 5t p3.3 t3out gpt1 timer t3 toggle latch output 12 i 5t p3.4 t3eud gpt1 timer t3 ext.up/down ctrl.input 13 i 5t p3.5 t4in gpt1 timer t4 input for count/gate/ reload/capture 14 i 5t p3.6 t3in gpt1 timer t3 count/gate input 15 i 5t p3.7 t2in gpt1 timer t2 input for count/gate/ reload/capture 18 o 5t p3.10 txd0 asc0 clock/data output (asyn./syn.) 19 i/o 5t p3.11 rxd0 asc0 data input (asyn.) or i/o (syn.) 20 o 5t p3.12 bhe ext. memory high byte enable signal o5t wrh ext. memory high byte write strobe 22 o 5t p3.15 clkout system clock output (=cpu clock) symbol pin number (tqfp) input (i) output (o) kind 1) function table 1 pin definitions 1 7/68 ST10R172l - pin description p4.0C p4.7 23-26 29-32- i/o 5t an 8-bit bidirectional i/o port. port 8 is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 4 can be used to output the segment address lines for external bus configuration. 23 o 5t p4.0 a16 least significant segment addr. line ... ... ... ... ... ... 26 o 5t p4.3 a19 segment address line 29 o 5t p4.4 a20 segment address line o 5t sspce1 chip enable line 1 30 o 5t p4.5 a21 segment address line o 5t sspce0 sspchip enable line 0 31 o 5t p4.6 a22 segment address line i/o 5t sspdat ssp data input/output line 32 o 5t p4.7 a23 most significant segment addr. line o 5t sspclk ssp clock output line rd 33 o 5t external memory read strobe. rd is activated for every exter- nal instruction or data read access. wr/ wrl 34 o 5t external memory write strobe. in wr-mode, this pin is acti- vated for every external data write access. in wrl-mode, this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in the syscon register for m ode selection. ready/ ready 35 i 5t ready input. active level is programmable. when the ready function is enabled, the selected inactive level at this pin dur- ing an external memory access will force the insertion of mem- ory cycle time waitstates until the pin returns to the selected active level. polarity is programmable. symbol pin number (tqfp) input (i) output (o) kind 1) function table 1 pin definitions 1 8/68 ST10R172l - pin description ale 36 o 5t address latch enable output. can be used for latching the address into external memory or an address latch in the multi- plexed bus modes. ea 37 i 5t external access enable pin. low level at this pin during and after reset forces the ST10R172l to begin instruction execu- tion out of external memory. a high level forces execution out of the internal rom. the ST10R172l must have this pin tied to 0. port0: p0l.0C p0l.7, p0h.0 - p0h.7 41 - 48 51 - 58 i/o 5t port0 has two 8-bit bidirectional i/o ports p0l and p0h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. for external bus configuration, port0 acts as address (a) and address/data (ad) bus in multiplexed bus modes and as the data (d) bus in demultiplexed bus modes. port1: p1l.0C p1l.7, p1h.0 - p1h.7 59- 66 67, 68 71-76 i/o 5t port1 has two 8-bit bidirectional i/o ports p1l and p1h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port1 acts as a 16-bit address bus (a) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. symbol pin number (tqfp) input (i) output (o) kind 1) function table 1 pin definitions demultiplexed bus modes data path width: 8-bit 16-bit p0l.0 C p0l.7: d0 C d7 d0 - d7 p0h.0 C p0h.7: i/o d8 - d15 multiplexed bus modes data path width: 8-bit 16-bit p0l.0 C p0l.7: ad0 C ad7 ad0 - ad7 p0h.0 C p0h.7: a8 C a15 ad8 C ad15 1 9/68 ST10R172l - pin description rstin 79 i 5t reset input with schmitt-trigger characteristics. resets the device when a low level is applied for a specified duration while the oscillator is running. an internal pullup resistor enables power-on reset using only a capacitor connected to v ss . with a bonding option, the rstin pin can also be pulled-down for 512 internal clock cycles for hardware, software or watchdog timer triggered resets rstout 80 o 5t internal reset indication output. this pin is set to a low level when the part is executes hardware-, software- or watchdog timer reset. rstout remains low until the einit (end of ini- tialization) instruction is executed. nmi 81 i 5s non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. if it is not used, nmi should be pulled high externally. p6.0- p6.7 82-89 i/o 5t an 8-bit bidirectional i/o port. port 6 is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 6 outputs can be configured as push/pull or open drain drivers. the following port 6 pins have alternate functions: 82 o 5t p6.0 cs0 chip select 0 output ... ... ... ... ... ... 86 o 5t p6.4 cs4 chip select 4 output 87 i 5t p6.5 hold external master hold request input (master mode: o, slave mode: i) 88 i/o 5t p6.6 hlda hold acknowledge output 89 o 5t p6.7 breq bus request output symbol pin number (tqfp) input (i) output (o) kind 1) function table 1 pin definitions 1 10/68 ST10R172l - pin description p2.8 C p2.11 90 - 93 i/o 5t port 2 is a 4-bit bidirectional i/o port. it is bit-wise programma- ble for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 2 outputs can be configured as push/pull or open drain drivers. the following port 2 pins have alternate functions: 90 i 5t p2.8 ex0in fast external interrupt 0 input ... ... ... ... ... ... 93 i 5t p2.11 ex3in fast external interrupt 3 input p7.0 C p7.3 94 - 97 i/o 5t port 7 is a 4-bit bidirectional i/o port. it is bit-wise programma- ble for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 7outputs can be configured as push/pull or open drain drivers. the following port 7 pins have alternate functions: 97 o 5t p7.3 pout3 pwm (channel 3) output rpd 40 i/o 5t input timing pin for the return from powerdown circuit and power-up asynchronous reset. v dd 7, 28, 38, 49, 69, 78 - po digital supply voltage. v ss 4, 27, 39, 50, 70, 77 - po digital ground. 1) the following i/o kinds are used. refer to electrical characteristics on page 31 for a detailed description. po: power pin 3t: 3 v tolerant pin (voltage max. respect to vss is -0.5 to vdd + 0.5) 5v: 5 v tolerant pin (voltage max. respect to vss is -0.5 to 5.5 only if chip is powered) 5s: 5 v tolerant and fail-safe pin (-0.5-5.5 max. voltage w.r.t. vss even if chip is not pow- ered). symbol pin number (tqfp) input (i) output (o) kind 1) function table 1 pin definitions 1 11/68 ST10R172l - functional description 2 functional description ST10R172l architecture combines the advantages of both risc and cisc processors with an advanced peripheral subsystem. the following block diagram overviews the different on- chip components and the internal bus structure. figure 2 block diagram st10 core 1kbyte dpram interrupt controller port 4 port 1 8-bit 2x8-bit port 0 2x8-bit port 2 4-bit por t 6 8-bit i/o cs(4:0) i/o hold hlda breq a(15:0) i/o, d(7:0) d(15:8), d(7:0) a(15:8), ad(7:0) ad(15:8), ad(7:0) i/o port 3 15-bit i/o exin(3:0) xtal1 dedicated pins asc gpt1/2 & pec i/o clkout, bhe/wrh , rxd0, txd0, t2in, t3in, t4in, t3eud, t3out, capin, t6out i t2eud, t4eud, t5in, t6in, t5eud, t6eud ea , ale, rd, wr/wrl , ready, nmi, rstin, rstout wdt xssp 4-bit i/o a(23:16), sspclk, sspdat, sspce(1:0) port 5 6-bit osc pll xtal2 port 7 4-bit pwm i/o pout3 1 12/68 ST10R172l - memory mapping 3 memory mapping the ST10R172l is a romless device, the internal ram space is 1 kbyte. the ram address space is used for variables, register banks, the system stack, the pec pointers (in 00fce0h - 00fcffh) and the bit-addressable space (in 00fd00h - 00fdffh). figure 3 memory map xssp data page 0 data page 1 data page 2 data page 3 000000h 004000h 008000h 00f000h 00f000h 00ffffh 000000h 001fffh 8k-byte 00ef00h 00efffh 256 byte internal memory 00f000h 00f200h 00fe00h 00ffffh sfr area (reserved) 1k-byte ram/sfr dpram / sfr area 4 k-byte system segment 0 64 k-byte external memory 00fe20h 00fe3fh 00ff20h 00ff3fh esfr area (reserved) 00f020h 00f03fh 00ff20h 00ff3fh ram 00fa00h block 1 block 0 1 13/68 ST10R172l - central processing unit 4 central processing unit the main core of the cpu contains a 4-stage instruction pipeline, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. most instructions can be executed in one machine cycle requiring 40ns at 50mhz cpu clock. the cpu includes an actual register context consisting of 16 wordwide gprs physically located in the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, one register bank may overlap others. a system stack of up to 1024 bytes is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are compared against the stack pointer value during each stack access to detect stack overflow or underflow. figure 4 cpu block diagram 16 16 internal ram 1kbyte r15 r0 general purpose registers r0 r15 mdh mdl barrel-shift mul./div.-hw bit-mask gen. alu 16-bit context ptr addrsel 1 addrsel 2 addrsel 3 addrsel 4 code seg. ptr. cpu idx0 idx1 qx1 qx0 qr0 qr1 sp stkov stkun exec. unit instr. ptr instr. reg 4-stage pipeline psw syscon buscon 0 buscon 1 buscon 2 buscon 3 buscon 4 data pg. ptrs 1 14/68 ST10R172l - interrupt and trap functions 5 interrupt and trap functions the architecture of the ST10R172l supports several mechanisms for fast and flexible response to the service requests that can be generated from various sources, internal or external to the microcontroller. any of these interrupt requests can be programmed to be serviced, either by the interrupt controller or by the peripheral event controller (pec). in a standard interrupt service, program execution is suspended and a branch to the interrupt service routine is performed. for a pec service, just one cycle is stolen from the current cpu activity. a pec service is a single, byte or word data transfer between any two memory locations, with an additional increment of either the pec source or the destination pointer. an individual pec transfer counter is decremented for each pec service, except in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. pec services are very well suited, for example, to the transmission or reception of blocks of data. the ST10R172l has 8 pec channels, each of which offers fast interrupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. via its related register, each source can be programmed to one of sixteen interrupt priority levels. once having been accepted by the cpu, an interrupt service can only be interrupted by a higher priority service request. for standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). software interrupts are supported by means of the trap instruction in combination with an individual trap (interrupt) number. 1 15/68 ST10R172l - interrupt and trap functions 5.1 interrupt sources source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number external interrupt 0 cc8ir cc8ie cc8int 60h 18h external interrupt 1 cc9ir cc9ie cc9int 64h 19h external interrupt 2 cc10ir cc10ie cc10int 68h 1ah external interrupt 3 cc11ir cc11ie cc11int 6ch 1bh gpt1 timer 2 t2ir t2ie t2int 88h 22h gpt1 timer 3 t3ir t3ie t3int 8ch 23h gpt1 timer 4 t4ir t4ie t4int 90h 24h gpt2 timer 5 t5ir t5ie t5int 94h 25h gpt2 timer 6 t6ir t6ie t6int 98h 26h gpt2 caprel register crir crie crint 9ch 27h asc0 transmit s0tir s0tie s0tint a8h 2ah asc0 transmit buffer s0tbir s0tbie s0tbint 11ch 47h asc0 receive s0rir s0rie s0rint ach 2bh asc0 error s0eir s0eie s0eint b0h 2ch pwm channel 3 pwmir pwmie pwmint fch 3fh ssp interrupt xp1ir xp1ie xp1int 104h 41h pll unlock xp3ir xp3ie xp3int 10ch 43h table 2 list of possible interrupt sources, flags, vector and trap numbers 1 16/68 ST10R172l - interrupt and trap functions 5.2 hardware traps exceptions or error conditions that arise during run-time are called hardware traps. hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can not normally be interrupted by standard or pec interrupts. the following table shows all of the possible exceptions or error conditions that can arise during run-time: exception condition trap flag trap vector vector location tr ap number trap priority reset functions: hardware reset reset 000000 h 00 h iii software reset reset 000000 h 00 h iii watchdog timer overflow reset 000000 h 00 h iii class a hardware traps: non-maskable interrupt nmi nmitrap 000008 h 02 h ii stack overflow stkof stotrap 000010 h 04 h ii stack underflow stkuf stutrap 000018 h 06 h ii class b hardware traps: undefined opcode undopc btrap 000028h 0a h i protected instruction fault prtflt btrap 000028h 0a h i illegal word operand access illopa btrap 000028h 0a h i illegal instruction access illina btrap 000028h 0a h i illegal external bus access illbus btrap 000028h 0a h i reserved [2c h C 3c h ][0b h C 0f h ] software traps trap instruction any [000000 h C 0001fc h ] steps of 4 h any [00 h C 7f h ] current cpu priority table 3 exceptions or error conditions 1 17/68 ST10R172l - parallel ports 6 parallel ports the ST10R172l provides up to 77 i/o lines organized into 7 input/output ports and one input port. all port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the output drivers of three i/o ports can be configured (pin by pin) for push/pull operation or open-drain operation by control registers. during the internal reset, all port pins are configured as inputs. all port lines have programmable alternate input or output functions associated with them. port0 and port1 may be used as address and data lines when accessing external memory, while port 4 outputs the additional segment address bits a23/19/17...a16 in systems where segmentation is enabled to access more than 64 kbytes of memory. port 6 provides optional bus arbitration signals (breq , hlda , hold ) and chip select signals. port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal bhe and the system clock output (clkout). port 5 is used for timer control signals. port 2 lines can be used as fast external interrupt lines. port 7 includes alternate function for the pwm signal. all port lines that are not used for these alternate functions may be used as general purpose i/o lines. 7 external bus controller all external memory accesses are performed by the on-chip external bus controller which can be programmed either to single chip mode when no external memory is required, or to the following external memory access modes: in the demultiplexed bus modes, addresses are output on port1 and data is input/output on port0/p0l, respectively. in the multiplexed bus modes both addresses and data use port0 for input/output. memory cycle time, memory tri-state time, length of ale and read write delay are programmable so that a wide range of different memory types and external peripherals can be used. up to 4 independent address windows can be defined (via addrselx / busconx register pairs) to access different resources with different bus characteristics. these address windows are arranged hierarchically where buscon4 overrides buscon3 etc. all accesses to locations not covered by these 4 address windows are controlled by buscon0. up to 5 external cs signals (4 windows plus default) can be generated to reduce external glue logic. access to very slow memories is supported by the ready function. a hold /hlda protocol is available for bus arbitration so that external resources can be shared with other bus masters. in slave mode, the slave controller can be connected to an- other master controller without glue logic. for applications which require less than 16 mbytes 16-bit data, demultiplexed 16-/18-/20-/24-bit addresses 16-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, demultiplexed 16-/18-/20-/24-bit addresses 1 18/68 ST10R172l - pwm module of external memory space, the address space can be restricted to 1 mbyte, 256 kbyte or to 64 kbyte. 8pwm module a 1-channel pulse width modulation (pwm) module operates on channel 3. the pulse width modulation module can generate up to four pwm output signals using edge-aligned or centre- aligned pwm. in addition, the pwm module can generate pwm burst signals and single shot outputs. the table below shows the pwm frequencies for different resolutions. the level of the output signals is selectable and the pwm module can generate interrupt requests. mode 0 edge aligned resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 20ns 195.3 khz 48.83khz 12.21khz 3.052khz 762.9hz cpu clock/64 1.28ns 3.052khz 762.9hz 190.7hz 47.68hz 11.92hz mode 1 center aligned resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 20ns 97.66khz 24.41khz 6.104khz 1.525khz 381.5hz cpu clock/64 1.28ns 1.525hz 381.5 hz 95.37hz 23.84hz 0hz table 4 pwm unit frequencies and resolution at 50mhz cpu clock 1 19/68 ST10R172l - general purpose timers 9 general purpose timers the gpts are flexible multifunctional timer/counters used for time-related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. the gpt unit contains five 16-bit timers, organized in two separate modules, gpt1 and gpt2. each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. 9.1 gpt1 each of the three timers t2, t3, t4 of the gpt1 module can be configured individually for one of four basic modes of operation: timer , gated timer , counter mode and incremental interface mode . in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable prescaler. in counter mode, the timer is clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the gate level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. table 5 gpt1 timer input frequencies, resolution and periods lists the timer input frequencies, resolution and periods for each pre-scaler option at 50mhz cpu clock. this also applies to the gated timer mode of t3 and to the auxiliary timers t2 and t4 in timer and gated timer mode the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). in incremental interface mode, the gpt1 timers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b by their respective inputs txin and txeud. direction and count signals are internally derived from these two input signals so that the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has output toggle latches (txotl) which changes state on each timer over-flow/ underflow. the state of this latch may be output on port pins (txout) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the contents of t2 or t4 triggered either by an external signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention. 1 20/68 ST10R172l - general purpose timers f cpu =50mhz timer input selection 000b 001b 010b 011b 100b 101b 110b 111b prescaler factor 8 16 32 64 128 256 512 1024 input frequency 6.25 mhz 3.125 mhz 1.5625 mhz 781 khz 391 khz 195 khz 97.5 khz 48.83 khz resolution 160ns 320ns 640ns 1.28 us 2.56 us 5.12 us 10.24 us 20.48 us period 10.49ms 20.97ms 41.94ms 83.88ms 168ms 336ms 672ms 1.342s table 5 gpt1 timer input frequencies, resolution and periods figure 5 gpt1 block diagram 2 n n=3...10 2 n n=3...10 2 n n=3...10 t2eud t2in cpu cl ock cpu cl ock cpu clock t3in t4in t3eud t4eud t2 mode t3 mode t4 mode gpt1 timer t2 gpt1 timer t3 gpt1 timer t4 t3otl reload capture u/d u/d reload capture interrupt request interrupt request interrupt request t3out u/d 1 21/68 ST10R172l - general purpose timers 9.2 gpt2 the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programmable by software or altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is supported by the output toggle latch (t6otl) of timer t6, which changes its state on each timer overflow/underflow. the state of t6otl may be used to clock timer t5, or may be output on a port pin t6out. the overflows/underflows of timer t6 reload the caprel register. the caprel register captures the contents of t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture procedure. this allows absolute time differences to be measured or pulse multiplication to be performedwithout software overhead. f cpu =50mhz timer input selection 000b 001b 010b 011b 100b 101b 110b 111b prescaler factor 4 8 16 32 64 128 256 512 input frequency 12.5 mhz 6.25 mhz 3.125 mhz 1.563 mhz 781 khz 391 khz 195 khz 97.6 khz resolution 80ns 160ns 320ns 640ns 1.28 us 2.56 us 5.12 us 10.24 us period 5.24ms 10.49ms 20.97ms 41.94ms 83.88ms 167.7ms 335.5ms 671ms table 6 gpt2 timer input frequencies, resolution and periods 1 22/68 ST10R172l - serial channels 10 serial channels serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an asynchronous/ synchronous serial channel (asc0) and a synchronous serial port (ssp). asc0 a dedicated baud rate generator sets up standard baud rates without oscillator tuning. 3 separate interrupt vectors are provided for transmission, reception, and erroneous reception. in asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. for multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). in synchronous mode, the asc0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the asc0. the asc0 always shifts the lsb first. a loop back option is available for testing purposes. a number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. a parity bit can be generated automatically on transmission, or checked on reception. framing error detection recognizes data frames with missing stop bits. an overrun error is generated if the last character received was not read out of the receive buffer register at the time the reception of a new character is complete.the table below lists figure 6 gpt2 block diagram 2 n n=2...9 2 n n=2...9 t5eud t5in cpu cl ock cpu clock t6in t6eud t5 mode t6 mode gpt2 timer t5 gpt2 ti mer t6 u/d interrupt request u/d gpt2 caprel t60tl toggle ff t6out capin reload interrupt request capture clear interrupt request 1 23/68 ST10R172l - serial channels various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate. ssp transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift clock which is generated by the ssp. the ssp can start shifting with the lsb or with the msb and is used to select shifting and latching clock edges, and clock polarity. up to two chip select lines may be activated in order to direct data transfers to one or both of two peripheral devices. when the ssp is enabled, the four upper pins of port4 can not be used as general purpose io. note that the segment address selection done via the system start-up configuration during reset has priority and overrides the ssp functions on these pins. s0brs = 0, f cpu = 50mhz s0brs = 1, f cpu = 50mhz baud rate (baud) deviation error reload value baud rate (baud) deviation error reload value 1562500 0.0% / 0.0% 0000 h / 0000 h 1041666 0.0% / 0.0% 0000 h / 0000 h 56000 +3.3% / -0.4% 001a h / 001b h 56000 +3.3% / -2.1% 0011 h / 0012 h 38400 +1.7% / -0.8% 0027 h / 0028 h 38400 +0.5% / -3.1% 001a h / 001b h 19200 +0.5% / -0.8% 0050 h / 0051 h 19200 +0.5% /-1.4% 0035 h / 0036 h 9600 +0.5% / -0.1% 00a1 h / 00a2 h 9600 +0.5% / -0.5% 006b h / 006c h 4800 +0.2% / -0.1% 0144 h / 0145 h 4800 0.0% / -0.5% 00d8 h / 00d9 h 2400 0.0% / -0.1% 028a h / 028b h 2400 0.0% / -0.2% 01b1 h / 01b2 h 1200 0.0% / -0.1% 0515 h / 0516 h 1200 0.0% / -0.1% 0363 h / 0364 h 600 0.0% / 0.0% 0a2b h / 0a2c h 600 0.0% / -0.1% 06c7 h / 06c8 h 190 +0.4% /+0.4% 1fff h / 1fff h 75 0.0% / 0.0% 363f h / 3640 h 127 +0.1% / +0.1% 1fff h / 1fff h table 7 commonly used baud rates, required reload values and deviation errors sspcks value synchronous baud rate 000 ssp clock = cpu clock divided by 2 25 mbit/s 001 ssp clock = cpu clock divided by 4 12.5 mbit/s 010 ssp clock = cpu clock divided by 8 6.25 mbit/s table 8 synchronous baud rate and sspcks reload values 1 24/68 ST10R172l - watchdog timer 11 watchdog timer the watchdog timer is a fail-safe mechanism which limits the malfunction time of the controller. the watchdog timer is always enabled after device reset and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. in this way, the chips start-up procedure is always monitored. the software must be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to maintain the watchdog timer, it will overflow generating an internal hardware reset and pulling the rstout pin low to reset external hardware components. the watchdog timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. the high byte of the watchdog timer register can be set to a pre-specified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. the table below shows the watchdog time range which for a 50mhz cpu clock rounded to 3 significant figures. 011 ssp clock = cpu clock divided by 16 3.13 mbit/s 100 ssp clock = cpu clock divided by 32 1.56 mbit/s 101 ssp clock = cpu clock divided by 64 781 kbit/s 110 ssp clock = cpu clock divided by 128 391 kbit/s 111 ssp clock = cpu clock divided by 256 195 kbit/s reload value in wdtrel prescaler for f cpu 2 (wdtin = 0) 128 (wdtin = 1) ff h 10.24 s 655 s 00 h 2.62 ms 168 ms table 9 watchdog timer range sspcks value synchronous baud rate table 8 synchronous baud rate and sspcks reload values 1 25/68 ST10R172l - system reset 12 system reset the following type of reset are implemented on the ST10R172l: asynchronous hardware reset: asynchronous reset does not require a stabilized clock signal on xtal1 as it is not internally resynchronized, it resets the microcontroller into its default reset state. asynchronous reset is required on chip power-up and can be used during catastrophic situations. the rising edge of the rstin pin is internally resynchronized before exiting the reset condition, therefore, only the entry to hardware reset is asynchronous. synchronous hardware reset (warm reset): a warm synchronous hardware reset is triggered when the reset input signal rstin is latched low and vpp pin is high. the i/os are immediately (asynchronously) set in high impedance, rstout is driven low. after rstin negation is detected, a short transition period elapses, during which pending internal hold states are cancelled and any current internal access cycles are completed, external bus cycles are aborted. then, the internal reset sequence is active for 1024 tcl (512 cpu clock cycles). during this reset sequence, if bit bdrsten was previously set by software (bit 3 in syscon register), rstin pin is driven low and internal reset signal is asserted to reset the microcontroller in its default state. note that after all reset sequence, bit bdrsten is cleared. after the reset sequence has been completed, the rstin input is sampled. when the reset input signal is active at that time the internal reset condition is prolonged until rstin becomes inactive. software reset: the reset sequence can be triggered at any time by the protected instruction srst (software reset). this instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system failure. as for a synchronous hardware reset, if bit bdrsten was previously set by software (bit 3 in syscon register), the reset sequence lasts 1024 tcl (512 cpu clock cycles), and drives the rstin pin low. watchdog timer reset: when the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle does not use ready , or if ready is sampled active (low) after the programmed waitstates. when ready is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. then the internal reset sequence is started. the watchdog reset cannot occur while the ST10R172l is in bootstrap loader mode. bidirectional reset: the bidirectional reset is activated by setting bit bdrsten (bit 3 in syscon register). this reset makes the watchdog timer reset and software reset externally visible. it is active for the duration of an internal reset sequences caused by a watchdog timer reset and software reset. therefore, the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 tcl. 1 26/68 ST10R172l - power reduction modes 13 power reduction modes two different power reduction modes with different levels of power reduction can be entered under software control. in idle mode the cpu is stopped, while the peripherals continue their operation. idle mode can be terminated by any reset or interrupt request. in power down mode both the cpu and the peripherals are stopped. power down mode can now be configured by software in order to be terminated only by a hardware reset or by an external interrupt source on fast external interrupt pins. all external bus actions are completed before idle or power down mode is entered. however, idle or power down mode is not entered if ready is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. 14 special function registers the following table lists all ST10R172l sfrs in alphabetical order. bit-addressable sfrs are marked with the letter b in column name. sfrs within the extended sfr-space (esfrs) are marked with the letter e in column physical address. an sfr can be specified by its individual mnemonic name. depending on the selected addressing mode, an sfr can be accessed by its physical address (using the data page pointers), or by its short 8-bit address (without using the data page pointers). name physical address 8-bit address description reset value addrsel1 fe18h 0ch address select register 1 0000h addrsel2 fe1ah 0dh address select register 2 0000h addrsel3 fe1ch 0eh address select register 3 0000h addrsel4 fe1eh 0fh address select register 4 0000h buscon0 b ff0ch 86h bus configuration register 0 0xx0h buscon1 b ff14h 8ah bus configuration register 1 0000h buscon2 b ff16h 8bh bus configuration register 2 0000h buscon3 b ff18h 8ch bus configuration register 3 0000h buscon4 b ff1ah 8dh bus configuration register 4 0000h caprel fe4ah 25h gpt2 capture/reload register 0000h cc8ic b ff88h c4h ex0in interrupt control register 0000h table 10 special functional registers 1 27/68 ST10R172l - special function registers cc9ic b ff8ah c5h ex1in interrupt control register 0000h cc10ic b ff8ch c6h ex2in interrupt control register 0000h cc11ic b ff8eh c7h ex3in interrupt control register 0000h cp fe10h 08h cpu context pointer register fc00h cric b ff6ah b5h gpt2 caprel interrupt control register 0000h csp fe08h 04h cpu code segment pointer register (read only) 0000h dp0l b f100h e 80h p0l direction control register 00h dp0h b f102h e 81h p0h direction control register 00h dp1l b f104h e 82h p1l direction control register 00h dp1h b f106h e 83h p1h direction control register 00h dp2 b ffc2h e1h port 2 direction control register -0--h dp3 b ffc6h e3h port 3 direction control register 0000h dp4 b ffcah e5h port 4 direction control register 00h dp6 b ffceh e7h port 6 direction control register 00h dp7 b ffd2h e9h port 7 direction control register -0h dpp0 fe00h 00h cpu data page pointer 0 register (10 bits) 0000h dpp1 fe02h 01h cpu data page pointer 1 register (10 bits) 0001h dpp2 fe04h 02h cpu data page pointer 2 register (10 bits) 0002h dpp3 fe06h 03h cpu data page pointer 3 register (10 bits) 0003h ebuscon b f10eh e 87h extended buscon register 0000h exicon b f1c0h e e0h external interrupt control register 0000h idchip f07ch e 3eh device identifier register 1101h idmanuf f07eh e 3fh manufacturer/process identifier register 0201h idmem f07ah e 3dh on-chip memory identifier register 0000h idprog f078h e 3ch programming voltage identifier register 0000h mdc b ff0eh 87h cpu multiply divide control register 0000h name physical address 8-bit address description reset value table 10 special functional registers 1 28/68 ST10R172l - special function registers mdh fe0ch 06h cpu multiply divide register C high word 0000h mdl fe0eh 07h cpu multiply divide register C low word 0000h odp2 b f1c2h e e1h port 2 open drain control register -0--h odp3 b f1c6h e e3h port 3 open drain control register 0000h odp6 b f1ceh e e7h port 6 open drain control register 00h odp7 b f1d2h e e9h port 7 open drain control register -0h ones ff1eh 8fh constant value 1s register (read only) ffffh p0l b ff00h 80h port 0 low register (lower half of port0) 00h p0h b ff02h 81h port 0 high register (upper half of port0) 00h p1l b ff04h 82h port 1 low register (lower half of port1) 00h p1h b ff06h 83h port 1 high register (upper half of port1) 00h p2 b ffc0h e0h port 2 register (4 bits) -0--h p3 b ffc4h e2h port 3 register 0000h p4 b ffc8h e4h port 4 register (8 bits) 00h p5 b ffa2h d1h port 5 register (read only) xxxxh p6 b ffcch e6h port 6 register (8 bits) 00h p7 b ffd0h e8h port 7register (4 bits) -0h pecc0 fec0h 60h pec channel 0 control register 0000h pecc1 fec2h 61h pec channel 1 control register 0000h pecc2 fec4h 62h pec channel 2 control register 0000h pecc3 fec6h 63h pec channel 3 control register 0000h pecc4 fec8h 64h pec channel 4 control register 0000h pecc5 fecah 65h pec channel 5 control register 0000h pecc6 fecch 66h pec channel 6 control register 0000h pecc7 feceh 67h pec channel 7 control register 0000h pp3 f03eh e 1fh pwm module period register 3 0000h name physical address 8-bit address description reset value table 10 special functional registers 1 29/68 ST10R172l - special function registers psw b ff10h 88h cpu program status word 0000h pw3 fe36h 1bh pwm module pulse width register 3 0000h pwmcon0 b ff30h 98h pwm module control register 0 0000h pwmcon1 b ff32h 99h pwm module control register 1 0000h pwmic b f17eh e bfh pwm module interrupt control register 0000h rp0h b f108h e 84h system start-up configuration register (rd. only) xxh s0bg feb4h 5ah serial channel 0 baud rate generator reload reg 0000h s0con b ffb0h d8h serial channel 0 control register 0000h s0eic b ff70h b8h serial channel 0 error interrupt control register 0000h s0rbuf feb2h 59h serial channel 0 receive buffer reg. (rd only) xxh s0ric b ff6eh b7h serial channel 0 receive interrupt control reg. 0000h s0tbic b f19ch e ceh serial channel 0 transmit buffer interrupt control reg 0000h s0tbuf feb0h 58h serial channel 0 transmit buffer register (wr only) 00h s0tic b ff6ch b6h serial channel 0 transmit interrupt control regis- ter 0000h sp fe12h 09h cpu system stack pointer register fc00h sspcon0 ef00h x --- ssp control register 0 0000h sspcon1 ef02h x --- ssp control register 1 0000h ssprtb ef04h x --- ssp receive/transmit buffer xxxxh ssptbh ef06h x --- ssp transmit buffer high xxxxh stkov fe14h 0ah cpu stack overflow pointer register fa00h stkun fe16h 0bh cpu stack underflow pointer register fc00h syscon b ff12h 89h cpu system configuration register 0xx0h 1) t2 fe40h 20h gpt1 timer 2 register 0000h t2con b ff40h a0h gpt1 timer 2 control register 0000h t2ic b ff60h b0h gpt1 timer 2 interrupt control register 0000h name physical address 8-bit address description reset value table 10 special functional registers 1 30/68 ST10R172l - special function registers note 1. the system configuration is selected during reset. note 2. bit wdtr indicates a watchdog timer triggered reset. t3 fe42h 21h gpt1 timer 3 register 0000h t3con b ff42h a1h gpt1 timer 3 control register 0000h t3ic b ff62h b1h gpt1 timer 3 interrupt control register 0000h t4 fe44h 22h gpt1 timer 4 register 0000h t4con b ff44h a2h gpt1 timer 4 control register 0000h t4ic b ff64h b2h gpt1 timer 4 interrupt control register 0000h t5 fe46h 23h gpt2 timer 5 register 0000h t5con b ff46h a3h gpt2 timer 5 control register 0000h t5ic b ff66h b3h gpt2 timer 5 interrupt control register 0000h t6 fe48h 24h gpt2 timer 6 register 0000h t6con b ff48h a4h gpt2 timer 6 control register 0000h t6ic b ff68h b4h gpt2 timer 6 interrupt control register 0000h tfr b ffach d6h trap flag register 0000h wdt feaeh 57h watc hdog timer register (read only) 0000h wdtcon ffaeh d7h watchdog timer control register 000xh 2) xp1ic b f18eh e c7h ssp interrupt control register 0000h xp3ic b f19eh e cfh pll unlock interrupt control register 0000h zeros b ff1ch 8eh constant value 0s register (read only) 0000h name physical address 8-bit address description reset value table 10 special functional registers 1 31/68 ST10R172l - electrical characteristics 15 electrical characteristics 15.1 absolute maximum ratings ? ambient temperature under bias ( t a ): ...................................................... -40c to +85 c ? storage temperature ( t st ):....................................................................... C 65 to +150 c ? voltage on v dd pins with respect to ground ( v ss ):..................................... C 0.5 to +4.0 v ? voltage on any pin with respect to ground ( v ss ): ................................ C0.5 to v dd +0.5 v ? voltage on any 5v tolerant pin with respect to ground ( v ss ): ....................... C0.5 to 5 .5 v ? voltage on any 5v fail-safe pin with respect to ground ( v ss ): ....................... C0.5 to 5 .5 v ? input current on any pin during overload condition: .................................. C10 to +10 ma ? absolute sum of all input currents during overload condition: .............................|100 ma| ? power dissipation:.....................................................................................................1.0 w note stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in 32/68 ST10R172l - electrical characteristics remarks on 5 volt tolerant (5t) and 5 volt fail-safe (5s) pins the 5v tolerant input and output pins can sustain an absolute maximum external voltage of 5.5v. however, signals on unterminated bus lines might have overshoot above 5.5v, presenting latchup and hot carrier risks. while these risks are under evaluation, observe the following se- curity recommendations: ? maximum peak voltage on 5v tolerant pin with respect to ground ( v ss )= +6 v ? if the ringing of the external signal exceeds 6v, then clip the signal to the 5v supply. power supply failure condition the power supply failure condition is a state where the chip is not supplied but is connected to active signal lines. there are several cases: ? 3.3v external lines on 3.3v (3t) pin on the non powered chip: ...............not acceptable ? 3.3v external lines on 5v tolerant (5t) pin on the non powered chip: ............. acceptable the 5v tolerant buffer do not leak: external signals not altered. no reliability problem. ? 3.3v external lines on 5v fail-safe (5s) pin on the non powered chip: ............ acceptable the 5v tolerant buffer do not leak: external signals not altered. no reliability problem. ? 5.5v external lines on 5v tolerant (5t) pin on the non powered chip: ............. acceptable for very short times only: the buffers do not leak (external signals not altered) but there is a fast degradation of the gate oxides in the buffers. the total maximum time under this stress condition is 2 days. this limits this configuration to short power-up/down sequences. for 10 year life time, the maximum duty factor is 1/1800 allowing e.g. a maximum stress duration of 48 seconds per day. ? 5.5v external lines on 5v fail-safe (5s) pin on the non powered chip: ............ acceptable ? 6v transient signals on 5v tolerant (5t) pin on the non powered chip: ...not acceptable ? 6v transient signals on 5v fail-safe (5s) pin on the non powered chip:.......... acceptable 1 33/68 ST10R172l - electrical characteristics 15.2 dc characteristics v dd = 3.3v 0.3v v ss = 0 v reset active t a = -40c to +85 c parameter symbol limit values unit test condition min. max. input low voltage v il sr C 0.3 0.8 v C input high voltage (all except rstin and xtal1) v ih sr 2.0 v dd + 0.3 vC input high voltage rstin, rpd v ih1 sr 0.6 v dd v dd + 0.3 vC input high voltage xtal1 v ih2 sr 0.7 v dd v dd + 0.3 vC output low voltage (ale, rd , wr , bhe , clkout, rstin ,rstout , csx) v ol cc C 0.4 v i ol = 4 ma output low voltage (all other outputs) v ol1 cc C 0.4 v i ol1 = 2 ma output high voltage ale, rd , wr , bhe , clkout, rstin ,rstout , csx ) v oh cc 2.4 C v i oh = C4 ma output high voltage 1) (all other outputs) v oh1 cc 2.4 C v i oh = C 2ma input leakage current (3t pins) i oz cc C 10 m a 0 v< v in < v dd input leakage current (5t, 5s pins) i oz1 cc C 10 100 7) m a m a 0 v< v in < v dd v dd < v in < 5.0v 7) rstin pull-up resistor 2) r rst cc 20 300 k w v in = 0 v read/write pullup current 3) i rwh 4) C-40 m a v out = 2.4 v read/write pullup current 3 i rwl 5) -500 C m a v out = 0.4 v ale pulldown current 3 i alel 4 40 C m a v out = 0.4 v ale pulldown current 3 i aleh 5 C500 m av out = 2.4 v port 6 (cs ) pullup current 3 i p6h 4 C-40 m av out = 2.4 v port 6 (cs ) pullup current 3 i p6l 5 -500 C m a v out = 0.4 v table 11 dc characteristics 1 34/68 ST10R172l - electrical characteristics port0 configuration current 3 i p0h 4 C-4 m av in = v ihmin i p0l 5 -50 C m av in = v ilmax rpd pulldown current 2 i rpd 5 100 500 m av out = v dd xtal1 input current i il cc C 20 m a 0 v < v in < v dd pin capacitance 6) (digital inputs/outputs) c io cc C 10 pf f = 1 mhz t a = 25 c power supply current i cc C15 + 2.5 * f cpu ma f cpu in [mhz] 7)) idle mode supply current i id C10 + 0.9 * f cpu ma rstin = v ih1 f cpu in [mhz] 7 power-down mode supply current i pd 8 C200 m a v dd = 3.6 v 9 1) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the resulting voltage comes from the external circuitry. 2) this specification is only valid during reset, or interruptible power-down mode, after recep- tion of an external interrupt signal that will wake up the cpu. 3) this specification is only valid during reset, hold or adapt-mode. port 6 pins are only affected if they are used for cs output and the open drain function is not enabled. 4) the maximum current may be drawn while the signal line remains inactive. 5) the minimum current must be drawn in order to drive the signal line active. 6) not 100% tested, guaranteed by design characterization. 7) supply current is a function of operating frequency as illustrated in figure 7 on page 35. this parameter is tested at v dd max and 50 mhz cpu clock with all outputs disconnected and all inputs at v il or v ih with an infinite execution of nop instruction fetched from external memory (16-bit demux bus mode, no waitstates, no memory tri-state waitstates, normal ale). 8) typical value at 25c = 20a. 9) this parameter is tested including leakage currents. all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v dd C 0.1 v to v dd , v ref = 0 v, all outputs (including pins con- figured as outputs) disconnected. parameter symbol limit values unit test condition min. max. table 11 dc characteristics 1 35/68 ST10R172l - electrical characteristics figure 7 supply/idle current vs operating frequency supply/idle current [ma] f cpu [mhz] 10 20 30 40 200 150 100 15 i ccmax i idmax 50 1 36/68 ST10R172l - electrical characteristics 15.3 ac characteristics test conditions ? input pulse levels: ........................................................................................... 0 to +3.0 v ? input rise and fall times (10%-90%):........................................................................ 2.5 ns ? input timing reference levels: ................................................................................. +1.5 v ? output timing reference levels: .............................................................................. +1.5 v ? output load: ................................................................................................... see figure 9 figure 8 input waveforms figure 9 output load circuit waveform 2.5ns 10% 90% 2.5 ns 10% 90% 0 v 3 v 1.5v 1.5v timing ref. points v ol v oh 1.5v 1.5v timing reference points ~ v ref i ol = 1ma i oh = 1ma from output under test c l = 50pf 3.3 v 1 37/68 ST10R172l - electrical characteristics figure 10 float waveforms v ol v oh timing reference v oh - 0.15 v points v ol + 0.15 v v load v load - 0.15 v v load +0.15 v ~ v ref i ol = 5 ma from output under test c l = 5 pf 3.3 v for timing purposes a port pin is no longer floating when a 150 mv change from load voltage occurs, but begins to float when a 150 mv change from the loaded voh/vol level occurs. cl is 5 pf for floating measurements only. i oh = 5 ma 1 38/68 ST10R172l - electrical characteristics 15.3.1 cpu clock generation mechanisms ST10R172l internal operation is controlled by the cpu clock f cpu . both edges of the cpu clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. the external timing (ac characteristics) specification therefore depends on the time between two consec- utive edges of the cpu clock, called tcl (see figure below). the cpu clock signal can be generated by different mechanisms. the duration of tcls and their variation (and also the external timing) depends on the f cpu generation mechanism. this must be considered when calculating ST10R172l timing. the cpu clock generation mechanism is set during reset by the logic levels on pins p0.15-13 (p0h.7-5). figure 11 cpu clock generation mechanisms p0.15-13 (p0h.7-5) cpu frequency f cpu = f xtal * f external clock input range 10- 50mhz notes 111 f xtal * 4 2.5 to 12.5 mhz default configuration 110 f xtal * 3 3.33 to 16.66 mhz 101 f xtal * 2 5 to 25 mhz table 12 cpu clock generation mechanisms tcl tcl tcl tcl f cpu f xtal f cpu f xtal phase locked loop operation (pll factor=4) direct clock drive tcl tcl f cpu f xtal prescaler operation 1 39/68 ST10R172l - electrical characteristics prescaler operation set when pins p0.15-13 (p0h.7-5) equal 001 during reset, the cpu clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f xtal and the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the period of the input clock f xtal . the timings listed in the ac characteristics that refer to tcls therefore can be calculated using the period of f xtal for any tcl. note that if the bit owddis in syscon register is cleared, the pll runs on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. direct drive when pins p0.15-13 (p0h.7-5) equal 011 during reset, the on-chip phase locked loop is disabled and the cpu clock is driven from the internal oscillator with the input clock signal. the frequency of f cpu directly follows the frequency of f xtal so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f xtal . the tcl timing below must be calculated using the minimum possible tcl which can be calculated by the formula: for two consecutive tcls the deviation caused by the duty cycle of f xtal is compensated so the duration of 2tcl is always 1/f xtal . therefore, the minimum value tcl min has to be used only once for timings that require an odd number of tcls (1,3,...). timings that require an even number of tcls (2,4,...) may use the formula: . 100 f xtal * 5 2 to 10 mhz 011 f xtal * 1 1 to 50 mhz direct drive 1) 010 f xtal * 1.5 6.66 to 33.33 mhz 001 f xtal / 2 2 to 100 mhz cpu clock via 2:1 prescaler 000 f xtal * 2.5 4 to 20 mhz 1) the maximum depends on the duty cycle of the external clock signal. the maxi- mum input frequency is 25 mhz when using an external crystal oscillator, but higher frequencies can be applied with an external clock source. p0.15-13 (p0h.7-5) cpu frequency f cpu = f xtal * f external clock input range 10- 50mhz notes table 12 cpu clock generation mechanisms tcl min 1 f xtal dc min dc ( = duty cycle ) = 2 tcl 1 f xtal = 1 40/68 ST10R172l - electrical characteristics note the address float timings in multiplexed bus mode (t 11 and t 45 ) use instead of . note that if the bit owddis in syscon register is cleared, the pll runs on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. oscillator watchdog (owd) when the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the pll circuitry. this oscillator watchdog operates as follows: after a reset, the oscillator watchdog is enabled by default. to disable the owd, set bit 4 of syscon register owddis. when the owd is enabled, the pll runs on its free-running frequency and increments the oscillator watchdog counter. on each transition of the xtal1 pin, the oscillator watchdog is cleared. if an external clock failure occurs, then the oscillator watchdog counter overflows (after 16 pll clock cycles). the cpu clock signal will be switched to the pll free-running clock signal, and the oscillator watchdog interrupt request (xp3int) is flagged. the cpu clock will not switch back to the external clock even if a valid external clock exits on xtal1 pin. only a hardware reset can switch the cpu clock source back to direct clock input. when the owd is disabled, the cpu clock is always fed from the oscillator input and the pll is switched off to decrease power supply current. phase locked loop for all other combinations of pins p0.15-13 (p0h.7-5) during reset the on-chip phase locked loop is enabled and provides the cpu clock. the pll multiplies the input frequency by the factor f which is selected via the combination of pins p0.15-13 (i.e. f cpu = f xtal * f). with every fth transition of f xtal the pll circuit synchronizes the cpu clock to the input clock. in this way, f cpu is constantly adjusted so it is locked to f xtal . the slight variation causes a jitter of f cpu which affects individual tcl duration.therefore, ac characteristics that refer to tcls must be calculated using the minimum possible tcl. the actual minimum value for tcl depends on the jitter of the pll. as the pll constantly adjusts its output frequency, it corresponds to the applied input frequency (crystal or oscillator). the relative deviation for periods of more than one tcl is lower than for one single tcl. for a period of n * tcl the minimum value is computed using the corresponding deviation d n : tcl max 1 f xtal dc max = tcl min tcl min tcl nom 1 d n 100 C () = d n 4 n 15 C () % [] = 1 41/68 ST10R172l - electrical characteristics where n = number of consecutive tcls and 1 n 40. so for a period of 3 tcls (i.e. n = 3): and pll jitter is an important factor for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. for slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. figure 12 approximated maximum pll jitter d 3 4315 C = 3,8% = 3 tcl min 3 tcl nom 1 3,8 100 C () = 3 tcl nom 0,962 36.07nsec @fcpu=50mhz () = 32 16 8 4 2 1 2 3 4 max.jitter [%] n this formula is valid for 1 43/68 ST10R172l - electrical characteristics 15.3.3 multiplexed bus v dd = 3.3 v 0.3 v v ss = 0 v t a = -40c to +85 c c l = 50 pf ale cycle time = 6 tcl + 2 t a + t c + t f (60 ns at 50-mhz cpu clock without waitstates) parameter symbol max. cpu clock = 50 mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. ale high time t 5 cc 7 + t a C tcl - 3 + t a Cns address (p1, p4), bhe setup to ale t 6 cc 3 + t a C tcl - 7 + t a Cns address (p0) setup to ale t 6m cc 5 + t a C tcl - 5 + t a Cns address hold after ale t 7 cc 5 + t a C tcl - 5 + t a Cns ale falling edge to rd , wr (with rw-delay) t 8 cc 5 + t a C tcl - 5 + t a Cns ale falling edge to rd , wr (no rw-delay) t 9 cc -5 + t a C -5 + t a Cns address float after rd , (with rw-delay) 1) t 10 cc C 5 1 C 5 1 ns address float after rd , (no rw-delay) 1 t 11 cc C 15 1 C tcl + 5 1 ns rd , wr low time (with rw-delay) t 12 cc 13 + t c C 2tcl - 7+ t c Cns rd , wr low time (no rw-delay) t 13 cc 23 + t c C 3tcl - 7 + t c Cns rd to valid data in (with rw-delay) t 14 sr C 5 + t c C 2tcl - 15 + t c ns rd to valid data in (no rw-delay) t 15 sr C 15 + t c C 3tcl - 15 + t c ns ale low to valid data in t 16 sr C 15 + t a + t c C 3tcl - 15 + t a + t c ns address to valid data in t 17 sr C 20 + 2 t a + t c C 4tcl - 20 + 2 t a + t c ns table 14 multiplexed bus 1 44/68 ST10R172l - electrical characteristics data hold after rd rising edge t 18 sr 0 C0 C ns data float after rd rising edge 12)) t 19 sr C 15 + t f 2 C 2tcl - 5 + t f 2 ns data valid to wr t 22 cc 13 + t c C 2tcl - 7 + t c Cns data hold after wr t 23 cc 13 + t f C 2tcl - 7+ t f Cns ale rising edge after rd , wr t 25 cc 10 + t f C 2tcl - 10 + t f Cns address hold after rd , wr t 27 cc 10 + t f C 2tcl - 10 + t f Cns latched cs setup to ale t 38 cc -7 + t a 3 + t a -7 + t a 3 + t a ns unlatched cs setup to ale t 38u cc 3 + t a C tcl - 7 + t a Cns latched cs low to valid data in t 39 sr C 13 + t c + 2 t a C 3tcl - 17 + t c + 2 t a ns unlatched cs low to valid data in t 39u sr C 23 + t c + 2 t a C 4tcl - 17 + t c + 2 t a ns latched cs hold after rd , wr t 40 cc 20 + t f C 3tcl - 10 + t f Cns unlatched cs hold after rd , wr t 40u cc 10 + t f C 2tcl - 10 + t f Cns ale fall. edge to rdcs , wrcs (with rw delay) t 42 cc 7 + t a C tcl - 3 + t a Cns ale fall. edge to rdcs , wrcs (no rw delay) t 43 cc -3 + t a C -3 + t a Cns address float after rdcs (with rw delay) 1 t 44 cc C 3 1 C 3 1 ns address float after rdcs (no rw delay) 1 t 45 cc C 13 1 C tcl + 3 1 ns parameter symbol max. cpu clock = 50 mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. table 14 multiplexed bus 1 45/68 ST10R172l - electrical characteristics rdcs to valid data in (with rw delay) t 46 sr C 3 + t c C 2tcl - 17 + t c ns rdcs to valid data in (no rw delay) t 47 sr C 13 + t c C 3tcl - 17 + t c ns rdcs , wrcs low time (with rw delay) t 48 cc 13 + t c C 2tcl - 7+ t c Cns rdcs , wrcs low time (no rw delay) t 49 cc 23 + t c C 3tcl - 7+ t c Cns data valid to wrcs t 50 cc 10 + t c C 2tcl - 10 + t c Cns data hold after rdcs t 51 sr0C0 C ns data float after rdcs 1 2 t 52 sr C 13 + t f 2 C 2tcl - 7 + t f 2 ns address hold after rdcs , wrcs t 54 cc 10 + t f C 2tcl - 10 + t f Cns data hold after wrcs t 56 cc 10 + t f C 2tcl - 10 + t f Cns 1) output loading is specified using figure 10 (cl = 5 pf). 2) this delay assumes that the following bus cycle is a multiplexed bus cycle. if next bus cycle is demultiplexed, refer to demuxultiplexed equivalent ac timing. parameter symbol max. cpu clock = 50 mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. table 14 multiplexed bus 1 46/68 ST10R172l - electrical characteristics figure 13 external memory cycle: multiplexed bus, with/without read/write delay, normal ale data in data out address address t 38 t 10 ale csx bus p0 read cycle rd bus p0 write cycle wr , wrl , wrh t 5 t 16 t 39 t 40 t 25 t 27 t 18 t 14 t 22 t 23 t 12 t 8 t 8 t 6m t 19m clkout address a23-a16 (a15-a8) bhe t 17 t 6 t 7 t 9 t 11 t 13 t 15 t 16 t 12 t 13 address t 9 t 39u t 38u t 40u 1 47/68 ST10R172l - electrical characteristics figure 14 external memory cycle: multiplexed bus, with/without read/write delay, extended ale data out address data in address address ale rd write cycle wr wrl , wrh t 5 t 16 t 6m t 7 t 39 t 40 t 14 t 8 t 18 t 23 t 6d/b read cycle t 27 bus p0 bus p0 t 38 t 10 t 19m csx clkout t 25 t 17 t 9 t 11 t 15 t 12 t 13 t 8 t 10 t 9 t 11 t 12 t 13 t 22 a23-a16 (a15-a8) bhe t 40u t 39u t 38u 1 48/68 ST10R172l - electrical characteristics figure 15 external memory cycle: multiplexed bus, with/without read/write delay, normal ale, read/write chip select data in data out address address t 44 ale bus p0 read cycle rdcsx bus p0 write cycle wrcsx t 5 t 16 t 25 t 27 t 51 t 46 t 50 t 56 t 48 t 42 t 42 t 6m t 52m clkout address a23-a16 (a15-a8) bhe t 17 t 6b/d t 7 t 43 t 45 t 49 t 47 t 16 t 48 t 49 address t 43 1 49/68 ST10R172l - electrical characteristics figure 16 external memory cycle: multiplexed bus, with/without read/write delay, extended ale, read/write chip select data out address data in address address ale rdcsx write cycle wr wrl , wrh t 5 t 16 t 6m t 7 t 46 t 42 t 42 t 50 t 18 t 56 t 6d/b read cycle t 54 bus p0 bus p0 t 44 t 19m a23-a16 (a15-a8) bhe clkout t 25 t 17 t 43 t 45 t 47 t 48 t 49 t 49 t 43 t 48 t 44 t 45 1 50/68 ST10R172l - electrical characteristics 15.3.4 demultiplexed bus v dd = 3.3 v 0.3 v v ss = 0 v t a = -40c to +85 c c l = 50 pf ale cycle time = 4 tcl + 2 t a + t c + t f (40 ns at 50 mhz cpu clock without waitstates) parameter symbol max cpu clock 50mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. ale high time t 5 cc 7 + t a C tcl - 3 + t a Cns address (p1, p4), bhe setup to ale t 6 cc 3 + t a C tcl - 7 + t a Cns address setup to rd , wr (with rw-delay) t 80 cc 13 + 2t a C 2tcl - 7 + 2t a Cns address setup to rd , wr (no rw-delay) t 81 cc 3 + 2t a C tcl - 7 + 2t a Cns rd , wr low time (with rw-delay) t 12 cc 13 + t c C 2tcl - 7 + t c Cns rd , wr low time (no rw-delay) t 13 cc 23 + t c C 3tcl - 7 + t c Cns rd to valid data in (with rw-delay) t 14 sr C 5 + t c C 2tcl - 15 + t c ns rd to valid data in (no rw-delay) t 15 sr C 15 + t c C 3tcl - 15 + t c ns ale low to valid data in t 16 sr C 15 + t a + t c C 3tcl - 15 + t a + t c ns address to valid data in t 17 sr C 20 + 2 t a + t c C 4tcl - 20 + 2 t a + t c ns data hold after rd rising edge t 18 sr 0 C 0 C ns data float after rd rising edge (with rw-delay) 1) 2) t 20 sr C 15 + t f + 2 t a 2 C2tcl - 5 + t f + 2 t a 2 ns data float after rd rising edge (no rw-delay) 1 2 t 21 sr C 5 + t f + 2 t a 2 Ctcl - 5 + t f + 2 t a 2 ns data valid to wr t 22 cc 13 + t c C 2tcl - 7 + t c Cns table 15 demultiplexed bus 1 51/68 ST10R172l - electrical characteristics data hold after wr t 24 cc 5 + t f C tcl - 5 + t f Cns ale rising edge after rd , wr t 26 cc -5 + t f C -5 + t f Cns address hold after rd , wr t 28 cc 0 (no t f) -9+ t f ( t f>0) C 0 (no t f ) -9+ t f ( t f>0) Cns address hold after wrh t 28h cc -1 (no t f) -8 + t f ( t f>0) C -1 (no t f ) -8 + t f ( t f>0) Cns latched cs setup to ale t 38 cc -7 + t a 3 + t a -7 + t a 3 + t a ns unlatched cs setup to ale t 38u cc 3 + t a C tcl - 7 + t a Cns latched cs low to valid data in t 39 sr C 13 + t c + 2 t a C 3tcl - 17 + t c + 2 t a ns unlatched cs low to valid data in t 39u sr C 23 + t c + 2 t a C 4tcl - 17 + t c + 2 t a ns latched cs hold after rd , wr t 41 cc 3 + t f C tcl - 7 + t f Cns unlatched cs hold after rd , wr t 41u cc 0 (no t f) -7 + t f ( t f>0) C 0 (no t f ) -7 + t f ( t f>0) Cns address setup to rdcs , wrcs (with rw-delay) t 82 cc 13 + 2t a C 2tcl - 7 + 2t a Cns address setup to rdcs , wrcs (no rw-delay) t 83 cc 3 + 2t a C tcl - 7 + 2t a Cns rdcs to valid data in (with rw-delay) t 46 sr C 3 + t c C 2tcl - 17 + t c ns rdcs to valid data in (no rw-delay) t 47 sr C 13 + t c C 3tcl - 17 + t c ns rdcs , wrcs low time (with rw-delay) t 48 cc 11 + t c C 2tcl - 9 + t c Cns rdcs , wrcs low time (no rw-delay) t 49 cc 21 + t c C 3tcl - 9 + t c Cns data valid to wrcs t 50 cc 13 + t c C 2tcl - 7 + t c Cns parameter symbol max cpu clock 50mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. table 15 demultiplexed bus 1 52/68 ST10R172l - electrical characteristics data hold after rdcs t 51 sr 0 C0 C ns data float after rdcs (with rw-delay) 1 2 t 53 sr C 13 + t f + 2ta 2 C2tcl - 7 + t f + 2ta 2 ns data float after rdcs (no rw-delay) 1 2 t 68 sr C 3 + t f+ 2ta 2 Ctcl - 7 + t f + 2ta 2 ns address hold after rdcs , wrcs t 55 cc -5 + t f C -5 + t f Cns data hold after wrcs t 57 cc 3 + t f C tcl - 7 + t f Cns 1) output loading is specified using figure 10 with cl = 5 pf. 2) this delay assumes that the following bus cycle is a demultiplexed bus cycle and that the data bus will only be driven externally when the rd or rdcs signal becomes active. rw- delay and t a refer to the following bus cycle. if the following bus cycle is a muxtiplexed bus cycle, refer to equivalent multiplexed ac timing (which are still applicable due to automatic insertion an idle state (2tcl) when switching from demultiplexed to multiplexed bus mode. parameter symbol max cpu clock 50mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. table 15 demultiplexed bus 1 53/68 ST10R172l - electrical characteristics figure 17 external memory cycle: demultiplexed bus, with/without read/write delay, normal ale data in data out t 38 ale csx p0 bus (d15-d8) d7-d0 read cycle rd p0 bus (d15-d8) d7-d0 write cycle wr (l ), wrh t 5 t 16 t 39 t 41 t 18 t 14 t 22 t 12 clkout address a23-a16 (a15-a8) bhe t 17 t 13 t 15 t 12 t 13 t 21d t 20d t 81 t 80 t 26 t 24 t 39u t 38u t 41u t 28, t 28h t 6 t 80 t 81 1 54/68 ST10R172l - electrical characteristics figure 18 external memory cycle: demultiplexed bus, with/without read/write delay, extended ale address ale rd write cycle wr (l ), wrh t 5 t 16 t 39 t 41 t 14 t 24 t 6 t 38 t 20d csx clkout t 26 t 17 t 15 t 12 t 13 t 12 t 13 t 22 a23-a16 (a15-a8) bhe data in p0 bus (d15-d8) d7-d0 read cycle t 18 t 21d t 38u t 39u t 41u t 28 , t 28h data out t 80 t 81 t 80 t 81 p0 bus (d15-d8) d7-d0 1 55/68 ST10R172l - electrical characteristics figure 19 external memory cycle: demultiplexed bus, with/without read/write delay, normal ale, read/write chip select data in data out ale p0 bus (d15-d8) d7-d0 read cycle rdcsx p0 bus (d15-d8) d7-d0 write cycle wrcsx t 5 t 16 t 51 t 46 t 50 t 48 clkout address a23-a16 (a15-a8) bhe t 17 t 49 t 47 t 48 t 49 t 68d t 53d t 83 t 82 t 26 t 57 t 55 t 6 t 82 t 83 1 56/68 ST10R172l - electrical characteristics figure 20 external memory cycle: demultiplexed bus, no read/write delay, extended ale, read/write chip select address ale rdcsx write cycle wrcsx t 5 t 16 t 46 t 57 t 6 t 53d clkout t 26 t 17 t 47 t 48 t 49 t 48 t 49 t 50 a23-a16 (a15-a8) bhe data in p0 bus (d15-d8) d7-d0 read cycle t 51 t 68d t 55 data out t 82 t 83 t 82 t 83 p0 bus (d15-d8) d7-d0 1 57/68 ST10R172l - electrical characteristics 15.3.5 clkout and ready /ready v dd = 3.3 v 0.3 v v ss = 0 v t a = -40c to +85 c c l = 50 pf parameter symbol max. cpu clock = 50 mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. clkout cycle time t 29 cc 20 20 2tcl 2tcl ns clkout high time t 30 cc 5 C tcl C 5 C ns clkout low time t 31 cc 5 C tcl C 5 C ns clkout rise time 1) 1) measured between 0.3 and 2.7 volts t 32 cc C 3 1 C 3 1 ns clkout fall time 1 t 33 cc C 3 1 C 3 1 ns clkout rising edge to ale falling edge t 34 cc -3 + t a 5 + t a -3 + t a 5 + t a ns synchronous ready setup time to clkout t 35 sr 9 C 9 C ns synchronous ready hold time after clkout t 36 sr 0 C 0 C ns asynchronous ready low time t 37 sr 27 C 2tcl + 7 C ns asynchronous ready setup time 2) 2) these timings assure recognition at a specific clock edge for test purposes only. t 58 sr 9 C 9 C ns asynchronous ready hold time 2 t 59 sr 0 C 0 C ns async. ready hold time after rd , wr high (demulti- plexed bus) 3)2 3) demultiplexed bus is the worst case. for multiplexed bus, 2tcl should be added to the maximum values. this adds even more time for deactivating ready. 2t a and t c refer to the following bus cycle, t f refers to the current bus cycle. t 60 sr 0 0 + 2 t a + t c + t f 3 0tcl - 10 + 2 t a + t c + t f 3 ns table16clkout and ready /ready 1 58/68 ST10R172l - electrical characteristics 1 cycle as programmed, including mctc waitstates (example shows 0 mctc ws). 2 the leading edge of the respective command depends on rw-delay. 3ready (or ready) sampled high (resp. low) at this sampling point generates a ready controlled waitstate, ready (resp. ready) sampled low (resp. high) at this sampling point terminates the currently running bus cycle. 4ready (resp. ready) may be deactivated in response to the trailing (rising) edge of the corresponding command (rd or wr ). 5 if the asynchronous ready (or ready) signal does not fulfill the indicated setup and hold times with respect to clkout (e.g. because clkout is not enabled), it must fulfill t 37 in order to be safely synchronized. this is guaranteed, if ready is removed in response to the command (see note 4)). figure 21 clkout and ready /ready sync ready t 35 t 36 t 35 t 36 async ready t 58 t 59 t 58 t 59 t 37 3) 3) 5) t 60 4) see 6) 3) 3) clkout ale t 30 t 34 sync ready t 35 t 36 t 35 t 36 async ready t 58 t 59 t 58 t 59 waitstate ready mux/tristate 6) t 32 t 33 t 29 running cycle 1) t 31 t 37 3) 3) 5) command rd, wr t 60 4) 2) 7) 3) 3) 1 59/68 ST10R172l - electrical characteristics 6 multiplexed bus modes have a mux waitstate added after a bus cycle, and an additional mttc waitstate may be inserted here. for a multiplexed bus with mttc waitstate this delay is 2 clkout cycles, for a demultiplexed bus without mttc waitstate this delay is zero. 7 the next external bus cycle may start here. 1 60/68 ST10R172l - electrical characteristics 15.3.6 external bus arbitration v dd = 3.3 v 0.3 v v ss = 0 v t a = -40c to +85 c c l = 50 pf parameter symbol max. cpu clock = 50 mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. hold input setup time to clkout t 61 sr 15 C 15 C ns clkout to hlda high or breq low delay t 62 cc C 10 C 10 ns clkout to hlda low or breq high delay t 63 cc C 10 C 10 ns csx release t 64 cc C 15 C 15 ns csx drive t 65 cc -3 15 -3 15 ns other signals release t 66 cc C 15 C 15 ns other signals drive t 67 cc -3 15 -3 15 ns table 17 external bus arbitration 1 61/68 ST10R172l - electrical characteristics 1 the ST10R172l will complete the running bus cycle before granting bus access. 2 this is the first opportunity for breq to become active. 3 the cs outputs will be resistive high (pullup) after t 64 . figure 22 external bus arbitration, releasing the bus clkout hold t 61 hlda t 63 other signals t 66 1) csx (on p6.x) t 64 1) 2) breq t 62 3) 1 62/68 ST10R172l - electrical characteristics 1 this is the last chance for breq to trigger the regain-sequence indicated. even if breq is activated earlier, the regain-sequence is initiated by hold going high. please note that hold may also be de-activated without the ST10R172l requesting the bus. 2 the next ST10R172l driven bus cycle may start here. figure 23 external bus arbitration, (regaining the bus) clkout hold hlda other signals t 62 csx (on p6.x) t 67 t 62 1) 2) t 65 t 61 breq t 63 t 62 1 63/68 ST10R172l - electrical characteristics 15.3.7 external hardware reset v dd = 3.3 v 0.3 v v ss = 0 v t a = -40c to +85 c c l = 50 pf parameter symbol max. cpu clock = 50 mhz variable cpu clock 1/2tcl = 1 to 50 mhz unit min. max. min. max. sync. rstin low time 1) 1) on power-up reset, the rstin pin must be asserted until a stable clock signal is available (about 10...50 ms to allow the on-chip oscillator to stabilize) and until system start-up con- figuration is correct on port0 (about 50 m s for internal pullup devices to load 50 pf from v il min to v ih min). t 70 sr 50 C4 tcl + 10C ns rstin low to internal reset sequence start t 71 cc 4164 16 tcl internal reset sequence, (rstin internally pulled low) t 72 cc 1024 1024 1024 1024 tcl rstin rising edge to inter- nal reset condition end t 73 cc 4646tcl port0 system start-up configuration setup to rstin rising edge 2)) 2) the value of bits 0 (emu), 1 (adapt), 13 to 15 (clock configuration) are loaded during hardware reset as long as internal reset signal is active, and have an immediate effect on the system. t 74 sr 100 C 100 C ns port0 system start-up configuration hold after rstin rising edge t 75 sr 1616tcl bus signals drive from internal reset end t 76 cc 0 20 0 20 ns rstin low to signals release t 77 cc C 50 C 50 ns ale rising edge from inter- nal reset condition end t 78 cc 8888tcl async. rstin low time 1 t 79 sr 1500 C 1500 C ns table 18 external hardware reset 1 64/68 ST10R172l - electrical characteristics 1 the ST10R172l is reset in its default state asynchronously with rstin . the internal ram content may be altered if an internal write access is in progress. 2 on power-up, rstin must be asserted t 79 after a stabilized cpu clock signal is available. 3 internal pullup devices are active on the port0 lines, so - input level is high if the respec- tive pin is left open - or is low if the respective pin is connected to an external pulldown device. 4 the ST10R172l starts execution here at address 000000h. 5rstout stays active until execution of the einit (end of initialization) instruction. 6 activation of the io pins is controlled by software figure 24 external asynchronous hardware reset (power-up reset): vpp low rstin port1 (demux bus) t 76 port0 t 75 4) internal reset signal t 73 3) t 792) t 74 ale rd , wr rstout 5) other ios 6) t 77 t 78 1) 1 65/68 ST10R172l - electrical characteristics . 1 the pending internal hold states are cancelled and the current internal access cycle (if any) is completed. 2rstin pulled low by internal device during internal reset sequence. 3 the reset condition may ends here if rstin pin is sampled high after t 72 . 4 internal pullup devices are active on the port0 lines. their input level is high if the respective pin is left open, or is low if the respective pin is connected to an external pull- down device by resistive high (pullup) after t 64 . 5 the ST10R172l starts execution here at address 000000h. 6rstout stays active until execution of the einit (end of initialization) instruction. 7 activation of the io pins is controlled by software. figure 25 external synchronous hardware reset (warm reset): vpp high rstin t 70 port1 (demux bus) t 76 t 711) port0 t 75 5) internal reset signal t 73 4) t 722) t 74 3) ale rd , wr rstout 6) other ios 7) t 77 t 78 1 66/68 ST10R172l - electrical characteristics 15.3.8 synchronous serial port timing v cc = 3.3 v 0.3 v v ss = 0 v t a = -40c to +85 c c l = 50 pf parameter symbol max. baudrate = 25 mbd variable baudrate = 0.2 to 25 mbd unit min. max. min. max. ssp clock cycle time t 200 cc 40 40 4 tcl 512 tcl ns ssp clock high time t 201 cc 13 C t 200 /2 - 7 C ns ssp clock low time t 202 cc 13 C t 200 /2 - 7 C ns ssp clock rise time t 203 cc C 3 C 3 ns ssp clock fall time t 204 cc C 3 C 3 ns ce active before shift edge t 205 cc 13 C t 200 /2 - 7 C ns ce inactive after latch edge t 206 cc 33 47 t 200 - 7 t 200 + 7 ns write data valid after shift edge t 207 cc C 7 C 7 ns write data hold after shift edge t 208 cc 0 C 0 C ns write data hold after latch edge t 209 cc 15 25 t 200 /2 - 5 t 200 /2 + 5 ns read data active after latch edge t 210 sr 27 C t 200 /2 + 7 C ns read data setup time before latch edge t 211 sr 15 C 15 C ns read data hold time after latch edge t 212 sr 0 C 0 C ns table 19 synchronous serial port timing 1 67/68 ST10R172l - electrical characteristics 1 the transition of shift and latch edge of sspclk is programmable. this figure uses the falling edge as shift edge (drawn bold). 2 the bit timing is repeated for all bits to be transmitted or received. 3 the active level of the chip enable lines is programmable. this figure uses an active low ce (drawn bold). at the end of a transmission or reception the ce signal is disabled in sin- gle transfer mode. in continuous transfer mode it remains active. figure 26 ssp write timing figure 27 ssp read timing t 204 t 203 sspclk sspcex sspdat t 205 t 207 t 207 t 207 t 208 t 209 t 206 1st bit last bit 2nd bit t 200 t 201 t 202 1) 3) 2) t 211 sspclk sspcex sspdat t 209 t 206 last wr. bit lst.in bit 1) 3) 2) t 212 1st.in bit t 210 1 68/68 ST10R172l - package mechanical data 16 package mechanical data 17 ordering information information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com figure 28 package outline tqfp100 (14 x 14 mm) sales type temperature range package ST10R172lt1 0c to 70c tqfp100 (14x 14) ST10R172lt6 -40c to +85 c dim mm inches min typ max min typ max a 1.60 0.063 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 15.75 16.00 16.25 0.620 0.630 0.640 d1 13.90 14.00 14.10 0.547 0.551 0.555 d3 12.00 0.472 e 15.75 16.00 16.25 0.620 0.630 0.640 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 0.50 0.020 number of pins nd 25 ne 25 n 100 1 |
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